1. Field of the Invention
The invention relates to a phase lock loop, and in particular, to programmable loop gain factors to enhance the working range.
2. Description of the Related Art
A Phase lock loop (PLL) circuit is widely used in the communication area for the purpose of clock synchronous and clock synthesis. PLL is a kind of feedback control circuit. All feedback circuit should be designed carefully to make sure that the whole circuit is stable. If the circuit is unstable, the output clock frequency would vary periodically.
FIG. 1 shows a general block diagram of the phase locked loop (PLL), comprising a phase detector 102, a charge pump 104, a low pass filter (LPF) 106, a voltage controlled oscillator (VCO) 108 and a frequency modifier 110. A reference frequency fref is provided to the phase detector 102 as an initial condition. The phase detector 102 typically has two input terminals and two output terminals. The phases of the reference frequency fref and a feedback frequency c are compared by the phase detector 102 to output either an up signal VUP or a down signal VDOWN. For example, rising edges of the reference frequency fref and feedback frequency fback are compared. An up signal VUP is asserted when the rising edge of the reference frequency fref is detected while that of the feedback frequency fback is not. The up signal VUP will hold high until the rising edge of the feedback frequency fback is detected. Conversely, down signal VDOWN is asserted when the rising edge of the feedback frequency fback is detected while that of the reference frequency fref is not. Likewise, down signal VDOWN will hold high until the rising edge of the reference frequency fref is detected.
The charge pump 104 typically comprises a current source to pull or drain a current based on the up signal VUP and down signal VDOWN, such that a control voltage Vf is generated at the output end of the LPF 106.
The VCO 108 then generates an output clock signal fout based on the control voltage Vf output from the LPF 106. The frequency of the output clock signal fout can be expressed as:fout=K*Vf  (1),
where K is a constant. This equation implies that the output clock frequency of the VCO 108 is proportional to the input voltage of it. The output clock signal fout is also fed back to the frequency modifier 110. The frequency modifier 110 performs a frequency division to generate a feedback frequency fback having a frequency expressed as:fback=fout/M   (2),
where M is a loop factor equal or greater than 1. Consequently, a close loop is formed, and the PLL 100 is expected to be recursively converged to lock on a desired frequency. Parameters of the components within the PLL must be carefully designed to exhibit stability and effective convergence characteristics. Generally, a unity loop gain is desired for the loop to converge to a stable condition. The loop factor M is usually adjustable to increase the flexibility of PLL such that a wide range of desired frequency can by dynamically rendered. However, the loop factor M is inverse proportional to the loop gain of the PLL. When the loop factor M is adjusted, the loop gain may be biased away from unity, and stability of the loop is influenced, causing the convergence time undeterminable. It is possible that an inappropriate loop factor M would cause the PLL to oscillate, diverge, or converge slow. As the PLL is usually an essential component in communication systems, it is desirable to implement an enhanced design to overcome the loop gain issue.